Introduction to Self Timed Circuits

Lecturer: Ned Bingham

This course will cover the fundamentals of self-timed circuits including timing assumptions and guarantees, failure modes, pipeline structures, data encodings, conditional logic, internal memory, and non-deterministic behavior, hardware description languages for different layers of abstraction, and two design methodologies. It is designed with a bottom up approach, starting with circuitry and working its way up through more abstract representations. Background experience with programming is required, and circuit design is helpful but optional. The course is offered for free with the goal of building local expertise and community in VLSI, Computer Architecture, and Self-Timed Circuits.

There will be 24 sessions over 12 weeks, each session involves roughly 30 minutes of lecture and 30 minutes of exercises. A full toolset will be provided in the form of a docker container for Linux, facilitating both digital and analog simulation. Each session will be recorded and made available within 24 hours.

Set up the toolset

  1. On Ubuntu, install the package from apt: sudo apt install, the docker-ce package doesn't let you write files from within the container.
  2. Pull the development environment image: docker pull
  3. Clone the Toolset for Self Timed Circuits: git clone
  4. Clone the Lectures and Exercises: git clone
  5. Set up the toolset: source broccoli-cli/
  6. Download the Skywater 130nm PDK and Configuration Files
  7. Extract to your home directory: mkdir ~/tech; tar -xzvf sky130.tar.gz -C ~/tech
  8. Configure the technology directory location: export BCLI_TECH="$HOME/tech"
  9. Start the docker container for the toolset: bcli up

Digital and analog simulation

  1. Connect to the docker container for the toolset: bcli
  2. cd /host/async-course/lecture_1
  3. fill in e1.act
  4. compile: make e1
  5. run the digital simulation: prsim e1.prs
  6. source e1.rc
  7. exit
  8. run the analog simulation: cd e1
  9. prsim env.prs
  10. source prsim.rc
  11. exit


  1. Digital Logic and Production Rules (slides, video)
  2. Introduction to Self Timed Circuits (slides, video)
  3. Weak Condition Half Buffers (slides, video)
  4. Fundamental Concepts (slides, video)
  5. Pre-Charge Half Buffers (slides, video)
  6. Encoding Data (slides, video)

Templated Synthesis

  1. Multiple Requests (slides, video)
  2. Early Out and Stack Length (slides, video)
  3. Conditional Inputs and Outputs (slides, video)
  4. Internal Memory (slides, video)
  5. Protected Forward Drivers (slides, video)
  6. ACT Language (slides, video)

Formal Synthesis

  1. Handshake Expansion and Reshuffling (slides, video)
  2. Projection and Process Decomposition (slides, video)
  3. Simulation and State Elaboration (slides, video)
  4. State Conflicts and State Variable Insertion (slides, video)
  5. Guard Strengthening (slides, video)
  6. Bubble Reshuffling (slides, video)

Advanced Topics

  • Jackson, Sandra, and Rajit Manohar. Gradual synchronization. International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE, 2016.
  • Bingham, Ned, and Rajit Manohar. QDI constant-time counters. Transactions on Very Large Scale Integration Systems, volume 27 issue 1 pages 83-91. IEEE, 2018.
  • Bingham, Ned, and Rajit Manohar. A Systematic Approach for Arbitration Expressions. Transactions on Circuits and Systems I: Regular Papers, volume 67 issue 12 pages 4960-4969. IEEE, 2020.
  1. Exchange Channels (slides, video)
  2. Design Strategies (slides, video)
  3. Implementation Strategies (slides, video)
  4. Synchronization and Non-Deterministic Behavior (slides, video)
  5. Arbitration Expressions (slides, video)
  6. Asynchronous to Synchronous Interfacing (slides, video)